1. Field of the Invention
The present invention relates to: a method and an apparatus each capable of precisely measuring a so-called overlap length of a MISFET (i.e., Metal Insulator Semiconductor Field Effect Transistor), wherein the overlap length forms one of important physical device parameters required in carrying out a circuit simulation of the MISFET such as MOS (i.e., Metal Oxide Semiconductor) transistors and the like; and, further to a recording medium and a device model each carrying an extraction program for determining the overlap length.
2. Description of the Related Art
In the technical field of LSI memories, it takes much time and money to develop a real-world prototype circuit for a new MOS memory, or for realizing a change in a fabrication process such as diffusion processes and like processes of a conventional MOS memory each time such new MOS memory is designed and developed, or such change in the production process is carried out. Consequently, heretofore, in place of such building of the real-world prototype circuit of the new MOS memory in design and development, it has been performed a series of computer simulations in design and development of the new MOS memory.
Such series of the computer simulations comprise: a process simulation for extracting various process data such as impurity concentrations and like process data; a device simulation for extracting various device parameters such as an effective channel length (Leff) and the like on the basis of the process data obtained through the above process simulation; and, a circuit simulation in which an exact value of a drain current (Id) is determined on the basis of the device parametrers obtained through the above device simulation, and a circuit analysis program called "SPICE" (i.e., Simulation Program with Integrated Circuit Emphasis) works so that memory operations, flip flop operations and like operations are investigated.
The more the results of these simulations approarch the results of experiments, the less period of time a desired MOS memory requires in its development. Consequently, demand for precise simulation techniques is very high.
Now, this type of computer simulation will be described in detail.
When a circuit simulation is performed in memory operation or in flip flop operation with respect to a MOS memory newly designed or changed in its fabrication process, it is necessary to precisely extract the device parameters by previously conducting both the above-mentioned process simulations and the device simulations in order that the device model having been incorporated in the circuit simulation may reproduce the actual device characteristics. A conventional method for extracting the device parameters will be now described. FIG. 10 shows a circuit diagram equivalent to the arrangement of a MOS transistor. A device model of such a MOS ransistor is represented by the following equation (1) in which drain current (Id) is defined. EQU Id=f(p1, p2, . . . , pN, Vd, Vg, Vb) (1)
where (p1, p2 , . . . , pN) is a set of the device parameters; Vd is a drain voltage; Vg is a gate voltage; and, Vb is a substrate voltage. PA1 where Vg is a gate voltage (i.e., a between gate/source voltage); and, Vth is a threshold voltage (i.e., a critical value of the gate voltage between an ON and an OFF mode of the MOS transistor). EQU R=(.DELTA.Id/.DELTA.Vd).sup.-1 (4) PA1 where Vd is a drain voltage (i.e., a between drain/source voltage).
In general, the device parameters have physical quantities, for example such as: an effective channel length (Leff), gate length (L), channel width (W), threshold voltage (Vth), resistance (r.sub.0) of a diffusion layer (shown in FIG. 10); an effective mobility (.mu.e) of movable carriers depending on the gate voltage (Vg); and, the like. Of these parameters, the device dimensions such as the gate length (L), channel width (W) and like dimensions capable of being directly measured are previously determined, and, therefore previously removed from a group of unknown parameters being extracted. On the other hand, assuming that the characteristics of the actually measured device are represented by the following equation (2), extraction of general device parameters is defined as follows: namely, over the entire range of applied voltages which the equation (2) directs, device parameters (p1, p2, . . . , pN) are selected in a manner such that the characteristics of the device model coincide with those of the actually measured device. EQU Id=g(Vd, Vg, Vb) (2)
More specifically, when the values of the above two equations (1) and (2) each at the i-th one of M pieces of applied voltages used in measurement are defined to be fi and gi, respectively, the above device parameters (p1, p2, . . . , pN) are selected so as to make the squared error E=.SIGMA.(fi-gi).sup.2 minimum. In this derivation, generally a so-called "method of iteration" is used with the use of the above-mentioned "SPICE". In this "method of iteration": at first, trial initial values of the device parameters (p1, p2, . . . , pN) are provided; and, thereafter, these device parameters (p1, p2, . . . , pN) starting therefrom are repeatedly rewritten until their variations assume very small values.
However, when this "method of iteration" is merely applied to the device parameters (p1, p2, . . . , pN), the thus extracted values tend to become abnormal from a physical point of view in spite of their inherent physical quantities. This is because: irrespective of the fact that the device model represented by the equation (1) does not completely coincide with the actual device in characteristics, a large number of the device parameters are forcibly determined on the basis of delicate differences between the equation (1) and the measured values.
When the device model is defined by the device parameters which are nonsense from a physical point of view, the characteristics of the device model when these device parameters are varied differ from those of the actual device. Particularly, with respect to the dependency of the characteristics on the gate length, the device model differs from the actual device, which poses a serious problem. In other words, as for the device parameters extracted from the device having the gate length L1, when the device has its gate length L1 replaced with another value L2, the characteristics of this device differ from those of an actual device having the gate length L2.
In order to cover the above deficiency, as for the device parameters which are important from a physical point of view, it is often performed to separately determine these important device parameters before the "method of iteration" is applied to the device parameters. As one of these importance device parameters, it is possible to enumerate the overlap length (.DELTA.L). Here, definition of the overlap length (.DELTA.L) is made as shown in FIG. 11. More specifically, through the overlap length (.DELTA.L) a gate electrode 81 overlaps both a source diffusion layer 82 and a drain diffusion layer 83.
Incidentally, as shown in FIG. 11, the effective channel length (Leff) is equal to a distance between a source-side p-n junction and a drain-side p-n junction located in the surface of a silicon substrate 84. In other words, the effective channel length (Leff) is equal to a difference between the gate length (L) and the overlap length (.DELTA.L). Consequently, when the overlap length (.DELTA.L) is determined, it is possible to determine the effective channel length (Leff=L-.DELTA.L).
Heretofore, for example, as disclosed in Japanese Patent Laid-Open Nos. Sho54-2667 and Hei07-176740, derivation of the overlap length (.DELTA.L) has been made by measuring a channel resistance (i.e., a resistance between a source electrode and a drain electrode) R represented by the following equation (4) at each of various effective gate voltages Vge represented by the following equation (3) in each of a plurality of MOS transistors varying in gate length when a drain voltage Vd is very small: EQU Vge=Vg-Vth (3)
FIG. 12 shows a characteristic diagram of the MOSFET, illustrating the conventional method of derivation of the overlap length (.DELTA.L) of the MOSFET, more specifically, illustrating the dependency of the channel resistance (R) on the gate length (L) in the MOSFET at each of the effective gate voltages (ranging from Vge1 to Vge5), wherein: the channel width is equal to 10 .mu.m; and, a film thickness of the gate oxide film Tox is equal to 10 .mu.m in an n-type MOS transistor. In the characteristic diagram of the MOSFET shown in FIG. 12: each of plots shows each of measurement locations; and, a group of straight lines are a group of regression lines each calculated by interpolation through the so-called "the method of least squares" in a condition in which the effective gate voltages ranging of from Vge1 to Vge5 corresponding to a range of from 1.0 volt to 3.0 volts, respectively.
In an n-type MOS transistor shown in FIG. 11, when a positive voltage (Vge1) is applied to a gate electrode 81, minority carriers (i.e., electrons) are attracted from the p-region to the surface of this p-region (i.e., p-type silicon substrate) 84 underneath a gate oxide film 85. The higher the gate voltage increases (i.e., Vge1&lt;Vge2&lt;Vge3&lt;Vge4&lt;Vge5), the more the electrons are attracted to the surface of the silicon substrate 84. Consequently, as shown in FIG. 12, the channel resistance R decreases, and, eventually an n-type narrow region (i.e., n-type channel) is formed underneath the surface of the gate oxide film 85. On the other hand, as shown in FIG. 12, a plurality of regression lines corresponding to the effective gate voltages of from Vgel to Vge5 substantially converge on a single point (a, b).
The reason why the group of the regression lines converge on such a single point (a, b) is as follows: namely,
In the fabrication process of the n-type MOS transistor, as shown in FIGS. 13A and 13B, first of all, a gate electrode 81 made of polysilicon and the like is formed on the surface of p-type silicon substrate 84 through a gate oxide film 85. Then, by self-alignment of the thus formed gate electrode 81, an impurity 86 such as "As.sup.+ " and like impurities is ion-implanted into the surface of the p-type silicon substrate 84, as shown in FIG. 13A. In order to activate the impurity 86 thus ion-implanted, a thermal annealing process is conducted as shown in FIG. 13B. As a result, a source diffusion region 82 and a drain diffusion region 83 are formed in opposite sides of the gate oxide film 85, wherein each of the source and the drain diffusion regions 82, 83 is constructed of an n-type high concentration diffusion layer. In the above ion-implantation stage, as shown in FIG. 13A, though the impurity 86 does not enters a region underneath the gate oxide film 85, during the subsequent thermal annealing stage, the impurity 86 having been ion-implanted diffuses into the region underneath the gate oxide film 85, as shown in FIG. 13B. Due to this, the gate oxide film 85 partially overlaps both the source diffusion region 82 and the drain diffusion region 83; since the degree of such diffusion of the impurity 86 into the region underneath the gate oxide film 85 does not vary in a condition in which the concentration of the impurity thus ion-implanted and the annealing conditions are the same, the overlap length (.DELTA.L) does not vary irrespective of the gate length (L) as long as the formation conditions of the n-type high concentration diffusion layers are the same. Incidentally, this is true as to a p-type MOS transistor.
Consequently, when the gate length (L) is gradually decreased, the source diffusion region 82 is eventually brought into contact with the drain diffusion region 83 to cause, without fail, a phenomenon in which the effective channel length (Leff) becomes a value of zero, irrespective of the fact that the gate 81 is still remains. When the above phenomenon occurs, the channel resistance (R) becomes the sum of a resistance r.sub.0 /2 of the drain diffusion layer 83 not depending on the gate length (L) and a resistance r.sub.0 /2 of the source diffusion layer 82 not depending on the gate length (L). Consequently, as shown in FIG. 12, the group of the regression lines corresponding to the Vgel to the Vge5 converge on the single point the coordinate of which is represented by "(a, b)". The x-axis coordinate (i.e., "a") of the above convergent point (a, b) corresponds to the overlap length (.DELTA.L). On the other hand, the y-axis (b) of the convergent point (a, b) corresponds to the resistance r.sub.0 of the diffusion layer.
The problems to be solved by the present invention is as follows: namely, in recent years, the MOS memory tends to assume a finer- and higher-density geometry. Due to this, the MOS transistors used in such ,MOS memory tends to have its gate length (L) more shortened.
However, in the conventional derivation operation of the overlap length (.DELTA.L), when the gate length (L) decreases, the dependency of the channel resistance (R) on the gate length (L) loses its linearity, which makes it difficult for the group of the regression lines to converge on a single point. Due to this, it is difficult for the conventional derivation operation to determine an exact value of the overlap length (.DELTA.L). This is because: when the gate length (L) decreases, the "two dimensional effect" (i.e., two dimensional distribution of electric current density) which is one of the "short channel effect" becomes distinct, and, therefore not negligible.